HDL Design for 32 Port Real Time Tera Hertz (Tbps) Wi-Fi Router ASIC Soft IP Core for Complex Network-on-Chip Wireless Internet & Cloud Computing Applications

The Aim is to HDL Design Implementation of 32×32 Port Wi-Fi Router for Complex NOC Computing Applications like Internet and cloud computing networks. This router is the main component in Network on Chip, the advantage is very simple and reliable for High Speed Parallel Distributed Pipe Line Data Processing Computing technique and very suit for complex NOC Computing application products 3G, 4G wireless Mobile Computing like Tablets, IPhones, Epads, Notebook Computers. The Importance and Usage of the router is for reduction of number of NOC components and Internet & Cloud traffic networks Complexity and Dataloss. This paper focuses on the Architecture Design and Implementation, Verification of 32 Port Router ASIC Card. The Building Blocks are Buffering Registers, Demultiplexers, FIFOs, and Schedulers. This Router Architecture Simulated by Xilinx ISE 9.2i/Altera Quartus II Software. Code written by using VHDL/Verilog HDL Programming & Debugging Done By Advanced Xilinx/Alter a/Cypress FPGA Development Board.