Chip Warpage Induced by Tapered Through-Silicon Vias: A Numerical Analysis

This paper concerns chip warpage caused by thermal expansion mismatch between tapered copper (Cu) through-silicon vias (TSVs) and the surrounding silicon (Si) matrix. Systematic numerical finite-element modeling is performed to simulate the periodic array of Cu TSVs. It is demonstrated that significant chip curvature can develop as a result of the tapered TSV geometry. The effects of taper angle, diameter, and density of TSVs; wafer thickness; and intermediate layers between Cu and Si are investigated.