Network on chip based multi-function image processing system using FPGA

Multifunction parallel image processing systems use standard buses to do inter core communication. Faster and scalable approaches are needed to improve the throughput of the system, but for data heavy applications like Image Processing (IP) algorithms there is a need for constant data transfer between different functional blocks on chip. The solution would either be hardwired buses or controlled communication. Networks-On-Chip (NoC) present a systematic solution, and can succeed a hardwired bus solution in a scalable form. This paper presents a multifunction image processing system prototyped on a single reconfigurable platform. The different IP cores have been implemented keeping in mind on-the-fly processing times and frame rates. The different modules are interconnected using a Torus architecture NoC with an information heavy packet structure and capable of addressing multiple nodes simultaneously. The implementation was done using a low cost Spartan 6 FPGA. Frame rates for standard sizes and chip utilization has been reported.