Investigation of the impact of grain boundary on threshold voltage of 3-D MLC NAND flash memory

Three-dimensional (3-D) NAND flash technology has been attracting much attention in recent years, for it overcomes the challenges of scaling limitation faced by 2-D NAND flash and meets the demand of higher storage density and lower bit cost. Several 3-D NAND flash architectures has been proposed recently. [1-3] However, most of these structures have adopted poly-crystalline silicon (poly-Si) as the channel material, which has interface traps distributing along the random grain boundary (GB). Previous study has shown that these GB traps can cause the fluctuations in electrical characteristics and result in a wider distribution of threshold voltage (V
_th
) for NAND flash memory [4], [5], where only the intrinsic V
_th
of the memory structure is analyzed. In this paper, we utilize 3-D simulation to examine the impact of GB with various positions on V
_th
of different storage states in a multi-level cell (MLC) NAND flash memory.