Branch assertion and elimination

Branch instructions are major obstacles in realizing full instruction level parallelism. Prediction strategies have been employed to ease the burden brought about by these instructions. Even though high prediction accuracy is being achieved, there is much room for improvement. A new approach to branch handling, called branch assertion, is described. This approach will make prediction for some branches unnecessary. A technique to eliminate conditional and unconditional branches from the pipeline, called branch elimination, is also specified. The combination accomplishes zero-cycle branching.