Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I/sub g/ versus V/sub g/ characteristics for the p/sup +//pMOSFET are essentially identical to those for the n/sup +//nMOSFET; however, when measured in inversion, the p/sup +//pMOSFET exhibits much lower gate current for the same |V/sub g/|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p/sup +//pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p/sup +/-polysilicon gate; and (3) conduction band electron tunneling from the p/sup +/-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p/sup +//pMOSFET, with one of them dominating in a certain voltage range.