Efficient Timing Mismatch Correction for Low-Cost Digital-Mixing Transmitter

In this paper we present a novel digital predistortion method to eliminate the nonlinear timing mismatches, delay mismatch and duty cycle mismatch, in the in-phase and quadrature upconversion signals of a power-efficient digital transmitter architecture. This transmitter architecture has a separate digital-mixing stage before the digital-to-analog conversion, which halves the number of required current cells in the radio frequency digital-to-analog converter (RFDAC), but introduces a nonlinear performance impact of timing mismatches in the digital-mixing stage. This paper analyzes the inefficiency in deploying a classical look up table (LUT) predistortion scheme for this impairment. Then a much more effective predistortion scheme based on a run-time binary-tree descent searching scheme is proposed to tackle the problem. Simulation results show that, for both 64-QAM and 256-QAM modulation schemes, the error-vector-magnitude (EVM) can be improved from around -24 dB to less than -42 dB with a power-efficient implementation, which leaves substantial design margin for other nonidealities distorting the transmitted signal. The power consumption of the predistortion block, exploiting dynamic voltage scaling, is 5.52 mW when operating at a sampling rate of 600 Mega samples per second (MSPs) and scales to 3.25 and 1.48 mW when reducing the sample rate to 400 and 200 MSPs.