Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip

Self-heating and high-operating temperature are major concerns in 3-D-chip integration. In this paper, we leverage a 3-D test chip (WideIO dynamic random access memory on top of a logic die) equipped with temperature sensors and heaters to explore thermal effects and to develop advanced thermal modeling strategies suitable for complex 3-D-stacked circuits. We correlate temperature measurements with the power dissipated by the heaters using model learning techniques. Moreover, we defined a thermal basis function obtained using power and thermal data available from the on-chip sensors. This function can be used to predict temperatures at chip locations far from the temperature sensors and to infer the power dissipation at any location of the chip. In addition, the same thermal basic function can be used jointly with formal interpolation frameworks like radial basis function methods to effectively estimate the full-chip thermal map. Results show that this methodology outperforms existing interpolation approaches for sparse integrated sensors.