CESSIUM: a single component for implementing high data rates DSSS/CDMA interference cancellation receivers

Different code division multiple access (CDMA) receiver architectures have already been proposed such as the maximum-likelihood or the decorrelating detectors. However these architectures are too complex to be implemented. Some other solutions based on subtractive interference cancellation (IC), which meanwhile have better performance than conventional detectors, are particularly attractive for hardware implementation. After a description and comparison of different IC methods, this article focuses on the implementation of a parallel interference cancellation receiver. A dedicated integrated component (ASIC), called CESSIUM, which integrates, in a single chip, all the required functions for such architecture is then described.