Design of low impedance busbar for 10 kV, 100A 4H-SiC MOSFET short-circuit tester using axial capacitors

This paper discusses the design of a setup for short-circuit (SC) testing of 10 kV 10A 4H-SiC MOSFETs. The setup can achieve voltages up to 10 kV and currents in excess of 100A. The main objective during the design was to obtain low parasitic inductance throughout the setup, while at the same time, reduce the complexity and size of the setup by avoiding series connection of DC-link capacitor and by employing capacitors with voltage ratings above 10 kV. Obtaining a low inductance at such voltage levels is challenging, considering the required clearance distances, the lack of radial style capacitor rated for 10 kV on the market, the package design of CREE 10 kV 10 A 4H-SiC MOSFETs and the required space for the device heater. Ansys Q3D is used in order to extract the parasitic components from the design. Custom designed aluminum cans for 15 kV axial capacitors are used in order to minimize the inductance, with a symmetrical arrangement in order to provide optimal current sharing distribution. Busbar measurements verify the low inductive design of the DC-link. The measured inductance is also validated by means of Finite Element Method analysis and by experimental validation.