System level design of a pattern recognition system based on the Gabor wavelets

In this paper we will address the system level design of pattern recognition architectures. The system targeted uses Gabor wavelets for the multi-frequency and multi-scale analysis of gray scale images. The macro-blocks or macro-functions architectures are developed in sight of the integration of a system-on-a-chip. We have faced two basic design problems. First, to which extent the algorithms can be simplified to fit a hardware implementation? Second, how the functionality will be partitioned to fit an optimal hardware/software system? To carry out these operations we have relied on a design methodology taking into account the realization constraints early in the design stages. We used a fast cycle precise simulator to attempt and evaluate many hardware/software alternatives.