A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-$\mu{\rm m}$ CMOS for Medical Implant Devices

This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis of comparator offset voltages is made. Based on the analysis, the comparator is optimized by only adjusting transistor sizes without any particular offset cancellation. As a result, when the common-mode input voltage varies from 300 mV to 450 mV at a 0.6 V supply, the 3×σ offset voltage is optimized to be about 6 mV with a fluctuation of only 0.15 mV, as revealed by Monte Carlo simulations. A prototype of the proposed ADC was fabricated in 0.18 μm 1P6M CMOS technology, which occupies an active area of only 380×430 μm
²
. At a 0.6-V supply and 20 kS/s sampling rate, the ADC achieves an SNDR of 58.3 dB and a power consumption of 38 nW, resulting in a figure of merit (FOM) of 2.8 fJ/conversion-step.