A 6-bit 800MS/s flash ADC in 0.35μm CMOS

In this work, a 6-bit 800 MS/s flash analog-to-digital converter (ADC) is proposed. An optimized resistance ratio averaging scheme is applied to: (1) reduce the offset, nonlinearity, (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors. The proposed ADC is simulated by Hspice using 0.35 μm TSMC technology and shows 32.24 dB/45.9 dB SNDR/SFDR, 5.06 bits ENOB, and the low power consumption of 45.12 mW from a 3.3V supply.