Low-leakage architecture for embedded ROM

Register File (RF), Static Random Access Memory (SRAM) and Read Only Memory (ROM) arrays on SoCs comprise over 50% area and consumes substantial power on die. The On die ROM usage is increasing as there is an increased focus on IOTs, multi-core microprocessor for notebooks, 2-in-1s and mobile applications. Achieving high performance at low power specification need considerable innovation. Use of High Threshold Voltage (V
_th
) devices may not be the solution when targeting high performance designs. Further, as technology scales, leakage increases exponentially, which requires more aggressive low leakage power schemes.