Notice of Violation of IEEE Publication Principles: Reduction of synchronization latency using speculative techniques

Notice of Violation of IEEE Publication Principles

"Reduction of Synchronization Latency Using Speculative Techniques"
by K.Kiruthiga, S.S.Thamilselvi
in the Proceedings of the IEEE 2nd International Conference on Innovations in Information Embedded and Communication Systems (ICIIECS), March 2015

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles.

This paper duplicated text and figures from the two papers cited below. The original content was copied without attribution (including appropriate references to the original author(s) and/or paper titles) and without permission.

Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:

"Eliminating Synchronization Latency Using Sequenced Latching"
by Ghaith Tarawneh, Alex Yakovlev and Terrence Mak
in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 22, Number 2, February 2014, pp. 408-419

and

"Solutions and Application Areas of Flip-Flop Metastability"
by Ghaith Tarawneh
PhD Thesis, Newcastle University, August 2013


Modern multicore systems have a large number of components operating in different clock domains and communicating through asynchronous interfaces. These interfaces use synchronizer circuits, which guard against metastability failures but introduce latency in processing the asynchronous input. A speculative method helps to reduce synchronization latency by overlapping it with commutation cycles.