Techniques For The Trace-Driven Simulation Of Cache Performance

In contemporary computers, cache memories are interposed between processors and primary memories in order to decrease access time and bus traffic. Because the design of the cache is critical and the factors affecting its performance are complex, trace-driven simulation is widely used and studied. This paper surveys three interesting techniques for the trace-driven simulation of cache designs: stack analysis methodologies that make it possible to obtain performance measures for a wide variety of cache designs from a single run of the simulator, compression algorithms specifically tailored to memory reference traces, and an approach to parallel trace-driven simulation of multiprocessor caches that dramatically reduces the simulation's synchronization and thus its running time.