Hardware implementation of the SUMIS detector using high-level synthesis

In this paper we investigate the hardware implementation of the subspace marginalization with interference suppression (SUMIS) detector using high-level synthesis (HLS). SUMIS is a promising detection approach for multiple-input multiple-output (MIMO) systems, due to its fixed computational complexity and well-defined tradeoff between complexity and performance. Based on a SystemC implementation, the Xilinx Vivado HLS tool is used to implement the SUMIS algorithm on a Virtex-7 field programmable gate array (FPGA). By defining different macro- and micro-architectures we propose three hardware designs of the SUMIS algorithm and compare them in terms of area, speed, and energy (design space exploration (DSE)). Our investigations reveal that hardware design using HLS is a viable approach for rapid prototyping and DSE.