FPGA realization of GDFT-FB based channelizers

Efficient channelization in flexible, reconfigurable communications systems is an ongoing challenge. Our previous work has shown that designs based on the DFT modulated Filter Bank (DFT-FB) and its extension, the Generalized DFT modulated Filter Bank (GDFT-FB) appear to have good computational efficiency and to simplify filter bank design. In this work we examine the design and implementation of the fundamental DFT-FB and GDFT-FB on an FPGA in both critically sampled and oversampled variants. Solutions to various design issues are presented and the FPGA resource usage associated with a concrete example is presented.