Lithography-Aware Analog Layout Retargeting

Photolithographic defects during manufacture cannot only result in significant yield loss in digital integrated circuits, but are also deemed as an important factor in evaluating the quality of analog layouts. In this paper, we propose a graph-based lithography-aware analog layout retargeting methodology. We build up our fault model based on a classical defect size distribution function, geometrical critical area analysis, and probability of failure (POF). The objective of our algorithm is to minimize POF by intelligent redundant space allocation scheme during layout compaction. The optimizations handle the whole analog layout area by global wire widening, intradevice wire shifting (WS), and interdevice WS, which are achieved by updating the constraint-graph representation of the layout. Moreover, we propose an extra space allocation approach that can further reduce POF by an inconsiderably small chip-area compromise. The yield improvement and superior effectiveness of our algorithm are exhibited by retargeting operational amplifiers and being compared with a traditional linear programming-based layout compaction method and a well-known even wire distribution scheme.