Designing Testable Plas for both Offline Testing and Concurrent Error Detection

In this paper, we present an improved design of testable PLAs for offline testing and suggest a unified approach for both offline testing and Concurrent Error Detection (CED). This design offers a more efficient use of the additional hardware for designing testable PLAs. The additional hardware required includes an address decoder [1] to select or deselect the product lines of the PLA, a ripple counter to generate the address for the decoder, and a Totally Self Checking checker for the output lines of the PLA. The design requires only two additional pinouts on the chip in contrast to (log/sub 2/(m+1)+1) additional pinouts where m is the number of product lines in the PLA. The additional hardware used for CED is also effectively utilized during offline testing, and the design is suitable for built-in testing of PLAs. The test procedures cover all single mode stuck-at, bridging, and crosspoint faults.