Barrier material selection for TSV last, flipchip & 3D - UBM & RDL integrations

Wafer Level Packaging as Flip chip, Fan-in, 3D and TSV technologies are more and more widely used in the semiconductor industry as it provides many benefits: die and package shrinkage, more I/O, price reduction.... The multiplication of the applications forces the industry to use low temperature, low cost, high throughput and versatile processes and equipment. This also generates questioning about the metallurgy to be selected for both the barrier/seed for Redistribution Layer (RDL) and/or Under Bump Metallization (UBM). Different Titanium based barrier/copper seed stacks have been sputter deposited using a DC magnetron PVD chamber and studied to select the suitable layer to fulfill criteria like minimum copper diffusion risk, best adhesion and wet etch chemistries compatibility. The characterizations and trials performed on both blanket and patterned wafers highlight the influence of the barrier film process conditions, composition and microstructure (including Ti content, metal target life, air exposure contamination, wafer preparation...) on the copper diffusion at low anneal temperature and/or shear test adhesion. Finally, for some advanced products both copper pillars and wire-bonding may have to be used which force aluminum PADs to remain exposed during the barrier removal leading to a third requirement: high selectivity between aluminum and the Pillar's barrier layer during its wet etch process. It will be shown that the large market tendency to used more complex & expensive TiW films as glue layer could be challenged thanks to a specific chemistry composition used for the barrier/seed wet etch.