Effects of packaging on mechanical stress in 3D-ICs

In this work the mechanical stress induced in 3D stacks by different packaging process steps is studied. The 3D stacks used in this work are assembled using two identical dies containing a number of stress sensors which are designed and manufactured in 65nm technology. It is observed that the contribution of the package substrate and the die-attach process to the redistribution of mechanical stress inside the 3D stacked IC is more significant than the one of the EMC and that the influence of packaging on the shape and amplitude of local stress around the inter-die interconnects (micro-bumps) is not significant. These observations are supported by the measurements of stress done using micro-Raman spectroscopy and are correlated with the results of finite element modeling and with optical warpage measurements of different packaging configurations.