Low-current spin transfer torque MRAM

Spin Transfer Torque Magnetic Random Access Memory (MRAM) possesses a unique combination of high speed, high endurance, non-volatility, and small cell size. Among the emerging new memory technologies, including phase change memory, resistive random access memory, and conductive bridging random access memory, Spin Transfer Torque MRAM is the only candidate with the potential for unlimited endurance, since no atoms are moved during writing. This makes it the only potential candidate to replace dynamic random access memory (DRAM), when DRAM scaling comes to an end. DRAM is the ubiquitous working memory found in large quantities in nearly all computing systems. As DRAM is scaled below the 20 nm node, the capacitor on which the charge is stored needs to be made ever-taller, in order to maintain enough capacitance to store sufficient charge until the next refresh cycle. In addition to introducing significant process integration challenges, this also results in shorter charge storage time at advanced nodes, thus increasing the rate at which the DRAM needs to be refreshed. For a 64 Gb DRAM, it is predicted that the capacitor will leak so much that more than 40% of the time and almost half of the DRAM power will be spent on refreshing.[1] If the switching current for Spin Transfer Torque MRAM can be reduced below 10 uA, Spin Transfer Torque MRAM could replace DRAM below the 20 nm node. Write current largely determines the cost of Spin Transfer Torque MRAM, since the transistor and hence cell area must be sized large enough to source the write current. It is important to distinguish between several related switching currents. Physicists often speak of the switching current threshold, Ic0. The switching current is measured with slow pulses and extrapolated back to 1 ns. Theoretically, Ic0 corresponds to the switching threshold at zero temperature. A more technologically relevant parameter is Ic10ns, the array-average switching current for a 10 ns pulse. Since these measurements are usually single-shot measurements, this corresponds to a switching probability of about 0.5. However, this is not the write current, Iwrite, for which the transistor needs to be sized, since it does not take into account the additional current required to obtain reliable writing or the bit-to-bit distribution in switching current. For a 1-bit error correction code, a typical requirement for the probability of not switching is Pns = 1e-12 (this depends slightly on the size of the memory, the retention requirement, and the bit-to-bit distribution of activation energy). Measured data showed that the switching voltage increased from ∼ 0.35 V to ∼ 0.5 V in order to decrease the probability of not switching from Pns = 0.5 to Pns = 1e-12.[2] Furthermore, measurements on 500 junctions gave a standard deviation of about 4.5% of the mean switching voltage.[3] Keeping in mind that the above data was measured on large ∼ 100 nm junctions, we can use this data to make a rough estimate of Iwrite = (0.5/0.35)(1+6∗4.5%)Ic10ns, which takes into account writing 6 sigma junctions from a Gaussian distribution. Hence we can expect Iwrite to be roughly twice Ic10ns. If a minimum feature size FinFet can source roughly 20 uA, then the requirement on switching current is Ic10ns < 10 uA.