An efficient FPGA implementation of the Harris corner feature detector

In computer vision, the Harris corner feature detector is one of the most essential early steps in many useful applications such as 3-D reconstruction. However, if it is implemented in software, the resulting code is probably not able to be executed in real time under low cost mobile processors. This paper proposes an efficient hardware approach that offloads the repetitive feature extraction procedures into logic gates hence the solution is low cost to produce and low power to operate compared to its software counterpart. In this project, the system is built and tested on a popular prototyping FPGA (Field programmable Gate Arrays) platform (Zed-board) with a small FPGA device. The experiments and demos show that the speed and accuracy of the feature detector are good enough for many real world applications.