Straintronics: A leap toward ultimate energy efficiency of magnetic random access memories

Aggressive scaling of complementary metal?oxide?semiconductor (CMOS) technologies in the past decade has left circuit engineers with a plethora of design challenges. As the feature size in CMOS scales below 22 nm, static power dissipation due to multiple sources of leakage (weak inversion current, drain induced barrier lowering, gate induced drain leakage, gate tunneling, etc.) becomes significantly large in digital circuits. The supply voltage, on the other hand, does not scale down equally. Therefore, the shorter channel length along with a high supply voltage leads to a high leakage power dissipation. Integrated systems are facing an increasing leakage to active power ratio [1]. Leakage is more pronounced in low-speed applications, such as biomedical devices, where the performance is limited to a few megahertz [2]. Another obstacle, which is mainly a concern for high-speed applications, is the increasing energy density [3], which requires complicated cooling schemes and packaging. Furthermore, battery technologies are not growing as fast as CMOS technology, leaving large portable systems with a few microwatts of power to live on. The obstacles facing circuit designers call for novel solutions to enable the industry to push the integration density as prophesized by Moore?s law [4]. Alternative technologies need to be combined with CMOS to overcome the shortcomings of CMOS technologies.