Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains

As the number of frequency domains aggressively grows in today's systems-on-chip (SoCs), the delivery of high-delay test quality across numerous frequency domains while meeting test budgets assumes crucial importance. This paper proposes a method to explore the delay test quality tradeoffs across these domains, determining an optimal distribution of the test time budget across all domains while minimizing the overall SoC delay defect escape level. Satisfaction of this goal necessitates not only consideration of fault coverage but also of the distinct characteristics of each domain, such as frequency, path length distribution, scan length, and shift speed as well as full utilization of concurrent test support while remaining within the constraints of power thresholds to provide a reliable test environment. An optimization formulation as well as efficient test time allocation methods based on convexity and fast concurrent test planning algorithms are provided.