Design and verification of Ethernet, VME IP core using ACE and CDC

In today's verification field System-On-a-Chip (SOC) designs contain increased levels of functional and structural complexities. Different SOC's having various design blocks and those blocks are operated at different clock frequencies which causes CDC issues. The CDC issues are visualized through ACE using Blue Pearl Software Suite. In this paper we discuss about Advance Clock Environment (ACE) and Clock Domain Crossing (CDC) using Blue Pearl Software Suite (BPS) of Ethernet and VME(Voice Modulation Engine) IP Core.