A capacitive-loaded level shift circuit for improving the noise immunity of high voltage gate drive IC

A high voltage gate drive IC achieving the high dV
_S
/dt noise immunity up to 85V/ns and the allowable negative V
_S
swing to -12V at 15V supply voltage is proposed for the first time. The robust features are due to the presented capacitive loaded level shift circuit used in the gate driver. Measured and simulated results are performed to verify the electrical characteristics of the designed gate driver which is implemented in a 0.5um 600V Bipolar-CMOS-DMOS (BCD) technology.