Bridging Behavioral and Register-Transfer Synthesis

This paper considers register-transfer synthesis and optimization from a control-data flowgraph specification. In contrast to scheduling under resource constraints, we derive a register-transfer (RT) description without imposing constraints on resources. The initial RT-level description may seem to have an excessive number of functional units and multiplexors, however it will typically exhibit also high signal reconvergence. We demonstrate with non-trivial benchmark examples that regions of high signal reconvergence offer high resynthesis and optimization potential also at RT-level, producing standard cell realizations that are comparable and competitive with alternate approaches in all aspects: layout area, path delay and gate-level testability. Tradeoffs in resource allocation are examined at RT-level only after optimizing the initial description. The RT-level description we generate serves as a top-level input to OASIS, which expands it to the required data-path components, synthesizes all control specifications, performs test generation and global optimization by redundancy removal and submits the final standard cell netlist for automatic placement and routing.