Implementation Study of Single Photon Avalanche Diodes (SPAD) in $0.8~\mu\hbox{m}$ HV CMOS Technology

Single Photon Avalanche Diodes (SPAD) are known for their excellent timing performance which enables Time of Flight capabilities in positron emission tomography (PET). However, current array architectures juxtapose the SPAD with its ancillary electronics at the expense of a poor fill factor of the SPAD array. The 3D vertical integration of SPADs and readout electronics represents a solution to the aforementioned problem. Compared to systems with external electronics readout, 3D vertical integration reduces the SPAD interconnect parasitic capacitance while greatly increasing the photosensitive area and improving overall performances. This paper presents the implementation of two SPAD structures designed for PET. The SPAD structures are designed using Teledyne DALSA high voltage (HV) CMOS technology targeted for a 3-dimensional single photon counting module (3DSPCM). SPAD with two types of guard ring (diffusion-based and virtual guard ring) are designed, fabricated and characterized. All structures are based on a p + anode in an n-well cathode and are implemented along with active quenching circuits for proper characterization. The results show that the contact distribution and the anode-cathode spacing impact the dark count rate (DCR). The design of SPADs with a diffusion guard ring have a DCR down to 3 s
^{- 1}
μm
^-2
at room temperature, afterpulsing probability of , timing resolution of 27 ps FWHM and PDE of 49% at 480 nm.