Reliability of HfAlOx in multi layered gate stack

This work has demonstrated a high quality HfO
₂
based gate stack by depositing HfAlO
_x
along with HfO
₂
in a layered structure. In order to get multifold enhancement of the gate stack quality both Al percentage and distribution were observed by varying the HfAlO
_x
layer thickness and it was found that <; 2% Al/(Al+Hf)% incorporation can result in up to 18% reduction in average EOT along with up to 41% reduction in gate leakage current as compared to the dielectric with no Al content. On the other hand, excess Al presence in the interfacial layer moderately increased the interface state density (D
_it
). When devices were stressed in the gate injection mode at a constant voltage stress, dielectrics with Al/(Hf+Al)% <; 2% showed resistance to stress induced flat-band voltage shift (ΔV
_FB
), and stress induced leakage current (SILC). The time dependent dielectric breakdown (TDDB) characteristics showed a higher charge to breakdown and an increase in the extracted Weibull slope (β) that further confirms an enhanced dielectric reliability for devices with <; 2% Al/(Al+Hf)%.