Positive-bias temperature instability (PBTI) of GaN MOSFETs

We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO
₂
or a composite SiO
₂
/Al
₂
O
₃
bilayer were studied. Our research has targeted the evolution of threshold voltage (V
_T
), subthreshold swing (S) and transconductance (g
_m
) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive V
_T
shift (ΔV
_T
) in both gate dielectrics under positive gate stress. In devices with a SiO
₂
gate oxide, we have found that ΔV
_T
is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO
₂
/Al
₂
O
₃
gate oxide, on the other hand, ΔV
_T
is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.