Impact of Variation in Nanoscale Silicon and Non-Silicon FinFETs and Tunnel FETs on Device and SRAM Performance

One of the key challenges in scaling beyond 10-nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage, V
_T
, inhibits V
_CC
scaling. In this paper, we present a comprehensive study of process variations and sidewall roughness (SWR) effects in silicon (Si) bulk n-/p-FinFETs, In
_0.53
Ga
_0.47
As bulk n-FinFETs, germanium (Ge) bulk p-FinFETs, and gallium antimonide-indium arsenide (GaSb-InAs) staggered-gap heterojunction n-/p-tunnel FETs (HTFETs) using 3-D Technology Computer Aided Design numerical simulations. According to the sensitivity study, FinFET and tunnel FET (TFET) device parameters are highly susceptible to fin width, W
_FIN
, and ultrathin body thickness, T
_b
, variations, respectively. TFETs show higher variation in device performance than FinFETs. A Monte Carlo study of SWR variation on nand p-FinFETs shows higher 3σ(VT Lin) of In
_0.53
Ga
_0.47
As bulk nand Ge bulk p-FinFETs than their Si counterparts. Furthermore, to study the variation impact on memory circuits, we simulate 6T and 10T static random access memory (SRAM) cells with FinFETs and HTFETs, respectively. The probability distribution of read failure in SRAM cells at different supply voltages, V
_CC
, shows that HTFETs require 10T SRAM cell architecture and less than 4% variation in T
_b
for their V
_CCmin
to approach 200 mV.