Delivering Parallel Programmability to the Masses via the Intel MIC Ecosystem: A Case Study

Moore's Law effectively doubles the compute power of a microprocessor every 24 months. Over the past decade, however, this doubling in performance has been due to the doubling of the number of cores in a microprocessor rather than clock speed increases. Perhaps nowhere is this more evident than with the Intel Xeon Phi coprocessor. This many core architecture exhibits not only massive inter-core parallelism but also intra-core parallelism via a wider SIMD width. However, for data-intensive applications, the bandwidth constraint of MIChinders the full utilization of computational resources, especiallywhen massive parallelism is required to process big data sets. Furthermore, the process of optimizing the performance on suchplatforms is complex and requires architectural expertise. To evaluate the efficacy of the Intel MIC ecosystem for "big data" applications, we use the Floyd-Warshall algorithmas a representative case study for graph applications. Ourstudy offers evidence that traditional compiler optimizations candeliver parallel programmability to the masses on the Intel XeonPhi platform. That is, developers can straightforwardly createmanycore codes in the Intel Xeon Phi ecosystem that deliversignificant speedup. The optimizations include reordering data-access patterns, adjusting loop structures, vectorizing branches, and using OpenMP directives. We start from the default serialalgorithm and apply the above optimizations one by one. Overall, we achieve a 281.7-fold speedup over the default serial version. When compared with the default OpenMP Floyd-Warshall parallel implementation, we still achieve a 6.4-fold speedup. We also observe that the identically optimized code on MIC can outperform its CPU counterpart by up to 3.2-fold.