Automatic synthesis of locally-clocked extended burst-mode AFSMs based on transparent latches

Controllers based on Synchronous Finite State Machines (SFSM) are components widely used in complex digital systems. These systems can present critical requirements, such as power consumption, robustness, performance, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new architecture, based in transparent latches, for implementing asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic. The asynchronous FSMs with local clock, implemented in the new architecture, are synthesized by SICARELO method. This method parts from a popular specification known as extended burst-mode (XBM) and uses the techniques of the synchronous paradigm to accomplish the synthesis. The new architecture was tested in a set of well-known benchmarks and compared with the AFSMs implemented through the standard architecture gRS, synthesized by the Miriã tool. Compared to Miriã tool, SICARELO tool achieved an average reduction of 12% in the number of state variables, 4% in the combinatorial logic of products and 15% in literals, although presenting a penalty of 79% on the number of latches. These results lead to a high potential of practical implementation of this method in actual applications.