Reconfigurable architecture design of FIR and IIR in FPGA

At the modern world digital signal processing (DSP) has turned into an enormously vital subject. A fundamental aspect of the digital signal processing is filtering. Filtering is a selective system which passes a certain range of frequency and attenuating the others frequency. Digital filtering is a powerful sector of DSP related works. A digital filter is a system which performs mathematical operations on a sampled or discrete time variant signal to shrink or enhance assured aspects of that signal. Digital filters are classified into finite impulse response (FIR) and infinite impulse response (IIR), which are based on the duration of the impulse response. FIR is a stable system and there is no feedback, but IIR has a feed forward path. This paper mainly focuses on the design of FIR and IIR filters of different forms like direct form or transposed of direct form in FPGA. FPGA is a system which can be used to implement the logical function because of its cost-effective properties. The proposed design algorithm of FIR and IIR is modeled in HDL and after the logically verified synthesize in the XST synthesis tool. The design performance of FIR and IIR is analyzed through the timing diagrams summary (time delay, minimum execution period etc.), HDL synthesis report and device utilization summary.