Feature detection for image analytics via FPGA acceleration

With the growth of multimedia data generation and consumption, image-based data analytics plays an increasingly important role in big data analytics systems. For image analytics, feature detection algorithms provide a foundation for a variety of image-based applications. These algorithms are typically computationally intensive and thus are good candidates for acceleration with field programmable gate arrays (FPGAs). In this paper, we investigate a Harris-Laplace variant of scale-invariant feature detection, a widely used image analytics algorithm, to demonstrate the capability of acceleration. Based on stream computing, we construct a fully pipelined implementation that can process one pixel per FPGA clock cycle. Our implementation significantly outperforms the existing published work. The proposed implementation adopts a single-precision floating-point representation and can detect the features of 640
$\times$
480-pixel images at 540 frames per second. This throughput is sufficient for multistream real-time video interpretation.