Replacement techniques for improving performance in sub-block caches

Recent advances in processor architecture have led to the introduction of sub-blocking to cache architectures. Sub-blocking reduces the tag area and power overhead in caches without reducing the effective cache size, by using fewer tags to index the full data RAM array. But they suffer from performance degradation due to cache pollution. We propose intelligent subblock cache replacement policies that use the valid state of individual sub-blocks in replacement decisions at the super-block level. Performance evaluations using Simplescalar toolset show improvement of up to 4.17% in SPEC2006 benchmarks.