Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation

A near-threshold voltage (V
_th
) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-V
_th
operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-V
_th
region. The recently proposed SRAM bit-cells with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-V
_th
region. This paper proposes a read buffer with adjusted the number of fins or V
_th
to resolve the problems in the near-V
_th
region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-V
_th
region.