Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction

The design of analog integrated circuits (ICs) is characterized by time-consuming and non-systematic iterations between electrical and physical design steps in order to achieve successful post-layout designs. This paper presents an innovative methodology for automatic optimization-based sizing of analog ICs that takes into consideration complete layout-related data for both circuit's geometric requirements, which are obtained from the real-time in-loop floorplan packing, and circuits' electrical performance that is evaluated using circuit simulator and considering accurate layout parasitic estimates. In order to boost the parasitic extraction efficiency, the need for expensive detailed layout generation, as found in previous state-of-the-art layout-aware sizing approaches, is here circumvented. However, the interconnect parasitic capacitances that are major contributors to performance degradation and on-die signal integrity problems, must be accurately accounted for. Therefore, an empirical-based parasitic extraction is performed on an early-stage layout obtained from the floorplan, computing the optimal electromigration-aware wiring topology and shortest rectilinear paths in-loop, without the need for detailed routing. Finally, the methodology is demonstrated for the UMC 130nm design process using well-known analog building blocks proving the generality, accuracy and fast execution of the proposed approach.