Modulo 2n + 1 squarer design for efficient hardware implementation

In this work, an efficient hardware architecture of modulo 2
ⁿ
+ 1 squarer is proposed and validated. The proposed modulo 2
ⁿ
+ 1 squarer use novel compressor designs and sparse tree adders as primitive building blocks for fast low-power operations in three major functional modules including partial products generation module, partial products reduction module and final stage addition module. The resulting modulo 2
ⁿ
+ 1 squarer has been implemented in standard CMOS (Complementary Metal-Oxide Semiconductor) cell technology and compared both qualitatively and quantitatively with the existing hardware implementations. The unit gate model analysis and the experimental results show that the proposed implementation is faster and consume less power than existing hardware implementations.