A 10-bit 20-MS/s dual-channel algorithmic ADC with improved clocking scheme

A 10-bit 20-MS/s dual-channel algorithmic analog-to-digital converter (ADC) using an improved clocking scheme is presented. The proposed ADC employs amplifier sharing technique with a conversion time scaling to reduce area and power. To achieve further improvement of conversion time scaling, dedicated MDAC sampling capacitors scaled with the accuracy requirement of each cycle are used. The ADC implemented in a 0.18µm CMOS process achieves 59.6dB SFDR and 54.3dB SNDR while consuming 8.96 mW per channel from a 1.8-V supply voltage.