A low-IF AGC amplifier for DSRC receiver

This paper proposes an auto-gain-control amplifier for DSRC IF receiver. The test chip was realized in 0.18-um CMOS technology and occupied an active area of 0.064 mm
²
. With a supply voltage of 1.8 V, the total power consumption was 10.5 mW. VGA exhibited a maximum gain of 82 dB and a dynamic range of 73 dB. For a 40-MHz of IF band, the ASK modulation index ranged from 0.23 to 1, and the data rate ranged from 10 kbps to 2.5 Mbps.