A comparative study on the implementation of reversible Binary Coded Decimal (BCD) Adder performance on Field Programmable Gate array (FPGA)

In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders can be implemented in a wide array of applications such as financial and commercial computations as most of the data stored and calculated are in decimal format. Hardware implementation of a BCD adder has been known to perform at least 100 times faster than its software counterparts. Current trends in reversible BCD adder consist of 4 major parts — 4-bit Adder, Correction and Detection Unit, and Modified 4-bit Adder. Designs were chosen based on overall design quantum cost, complexity, and estimated delays. The designs are then implemented on Altium Designer using Hardware Description Language(HDL) and verified on Xilinx Spartan 3AN and Altera Cyclone I FPGAs.