Implementation of PRINCE algorithm in FPGA

This paper presents a hardware implementation of the PRINCE block cipher in Field Programmable Gate Array (FPGA). In many security applications, the software implementations of cryptographic algorithms are slow and inefficient. In order to solve the problems, a new FPGA architecture was proposed to speed up the performance and flexibility of PRINCE algorithm. The concurrent computing design allows an encryption block data of 64 bits within one clock cycle, reducing the hardware area and producing a high throughput and low latency. It also showed high speed processing and consumed low power. To do this, firstly, the encryption, decryption and key schedule are all implemented with small hardware resources, Next, an efficient hardware architectural model for PRINCE algorithms was developed using very high speed integrated circuit hardware description language (VHDL). Finally, the VHDL design for PRINCE algorithm was synthesized in FPGA boards. Two FPGA boards were used in this study, which are Virtex-4 and Virtex-6. The results show a throughput of 2.03 Gbps and efficiency of 2.126 Mbps/slice for Virtex-4, whereas a throughput of 4.18 Gbps and efficiency of 8.681 Mbps/slice for Virtex-6.