High temperature influence on analog parameters of Bulk and SOI nFinFETs

This paper presents an experimental analysis of the high temperature influence on the main digital and analog parameters in triple gate nFinFET devices processed on both Bulk and Silicon-On-Insulator (SOI) substrates. Regarding the studied analog parameters, there was no significant variation as the temperature increases, at least for the temperature from 25°C to 150°C. Moreover, the SOI FinFET (SFF) presented lower intrinsic voltage gain (A
_v
) than the Bulk FinFET (BFF) for wide fins, due to the parasitic back conduction for all temperature range. Additionally, the drain induced barrier lowering (DIBL) of SFF present a large increase with temperature. It suggests that the drain electrical field penetration into the channel region for SFF is less efficient when compared to the ground plane (GP) for BFF. On the other hand, the BFF devices presented a larger threshold voltage variation as the temperature rises caused by the variation of the confined electron current depth into the channel region, which is strongly influenced by the ground plane concentration as observed by 3D simulation.