Effects of Dit-induced degradation on InGaAs/InAlAs Nanowire Superlattice-FET using Al2O3 and HfO2/La2O3 as gate stacks

In this work we investigate the effects of different interface trap density distributions (D
_it
) on the electrical and power performances of a Gate-All-Around In
_0.53
Ga
_0.47
As/In
_0.52
Al
_0.48
As Nanowire Superlattice-FETs (GAA NW SL-FET) using Al
₂
O
₃
and HfO
₂
/La
₂
O
₃
as gate dielectrics. This analysis shows that a high At content at the high-K/InGaAs interface causes degradation of the subthreshold characteristics and drive current, but also an improvement of the OFF-state leakage. However, even in the presence of traps, dynamic energy/power consumption of the Al
₂
O
₃
-based SL-FET is predicted to be at least 2× lower than all the ITRS requirements for the 9nm technology node, while HfO
₂
/La
₂
O
₃
-based device is perfectly suitably for Low-Standby-Power application, at fixed supply voltage V
_dd
= 0.4 V.