SAT based low power scheduling and module binding with clock gating

In today's circuit designs, with increasing density of devices and fast augmentation of clock frequencies, low-power design is a crucial issue. Clock power devours 60-70 percent of aggregate chip power. This is because power is directly proportional to voltage and also the frequency of the clock when the modules are unused. The purpose of this work is to explore the module binding to reduce the clock tree power based on clock gating. Based on the perception that module binding in high level synthesis has a vital impact on the power consumption of the gated clock tree, a satisfiability (SAT) based approach is proposed in this paper which is based on reduction of the activity pattern, especially with functional module binding. The scheduling and module binding is formulated as a satisfiability problem (SAT) and a PB-SAT (pseudo-Boolean) solver is utilized for discovering the optimal binding solution that minimizes the total power consumption because of the activity pattern.