Experimental Proof of the Drain-Side Dielectric Breakdown of HKMG nMOSFETs Under Logic Circuit Operation

Continuous CMOS logic switching results in a consecutive series of gate bias temperature instability and drain (OFF-state) stress. We also show that the asymmetric stress condition leads to a preferential breakdown at the drain side and that neither gate-only nor drain-only stress can reproduce this behavior. The findings are verified by the voltage ratio method as well as dc current-voltage measurements and are caused by trapping and detrapping under the alternating electric field.