Field programmable gate array design for an application specific signal processing algorithms

Field Programmable Gate Array (FPGA) architectures have emerged as an alternative means of implementing complex logic circuits providing rapid manufacturing turnaround time and low prototyping costs. This paper presents a new FPGA architecture suitable for the application specific signal processing algorithms and Wafer-Scale integration (WSI) Technology. The architecture must be designed for versatility, flexibility, high speed, improved logic density, and defect tolerance. The proposed FPGA architecture consists of 2 dimensional array of programmable logic elements based on look-up table, interconnection resources, and input/output (I/O) blocks. The architectural style is similar to the one used in XILINX FPGA architecture. A key variation from the commonly used FPGA is the dual switching scheme employed in the proposed architecture. The design methodology, the design tools, and results obtained by using a Segmented Channel Routing algorithm to map on it a 16 bit parallel multiplier, are presented.